14.22 CacheErr Register (27)
Figure 14-25 CacheErr Register Format for Primary Data Cache Errors
EW: set when CacheErr register is already holding the values of a previous error
EE: tag error on an inconsistent block
D: data array error (way1 || way0)
TA: tag address array error (way1 || way0)
TS: tag state array error (way1 || way0)
TM: tag mod array error (way1 || way0)
PIdx: primary cache virtual double word index, VA[13:6]
0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)
